Saturday, 21 September 2013

Previous GATE Questions on Diode - 2


Previous GATE Questions on Diode - 2 includes forward bias, reverse bias, V-I characteristics, static and dynamic resistance, effect of temperature on Io and diode voltage.



   1.       (a) Two ideal and identical (ideality factor ƞ = 1) junction diodes are connected in series as shown in figure.                [GATE'90] 



      Show that
 exp (eV1/KT)  +  exp (-eV2/KT) = 2
                                where V1 and V2 are the voltage drops across the diodes D1 and D2.
                   (b) Assuming that the current through the reverse biased diode is saturated at Io, calculate the Voltage drop across the forward biased diode. Assume KT = 26meV. 
    


   2.       Consider the circuit shown in figure (a). If the diode used here has the V-I characteristic as in figure (b), then the output waveform VO is                                                                                  [G’93]




   3.       Two identical silicon junction diodes, D1 and D2 are connected back to back as shown figure. The reverse saturation current , IS of each diode is 10-8 amps and the breakdown voltage is 50 volts. Evaluate the voltage VD1 and VD2 across the diode D1 and D2 by assuming KT/q to be 25mV.                                                                                                                                                         [GATE’95]



   4.       The static characteristic of an adequately forward biased PN junction is a straight line, if the plot is of                                                                                                                                                      [GATE’98]

a.       Log I   vs.   log V
b.      Log I   vs.   V
c.       I      vs.     log V
d.      I      vs.     V





   5.       For the circuit shown in figure, D1 and D2 are identical diodes with ideality factor of unity. The thermal voltage VT = 25mV.                                                                              [GATE'01]                                                                                                              

           a.        Calculate VF and VR
           b.       If the reverse saturation current , IS , for the diode is 1pA, then compute the current I through the circuit.




   6.       In the figure, a silicon diode is carrying a constant current of 1 mA. When the temperature of the diode is 200C, VD is found to be 700 mV. If the temperature rises to 400C, VD becomes approximately equal to                                                                                                                                           [GATE’02]




   7.       At 300oK, for a diode current of 1 mA, a certain germanium diode requires a forward bias of 0.1435 volts, where as a certain silicon diode requires a forward bias of 0.718 volts. Under the conditions stated above, the closest approximation of the ratio of reverse saturation current in germanium diode to that of silicon diode is                                                                                    [GATE’03]


a.       1
b.      5
c.       4 x 103
d.      8 x 103





    

8. In abrupt PN junction, the doping concentrations on the p-side and n-side are NA = 9 x 1016 /cm3 and ND = 1 x 1016 /cm3 respectively. The PN junction is reverse biased and the total depletion width is 3 µm. The depletion width on the p-side is 
                                                      [GATE’04]


a.       2.7 µm
b.      0.3 µm                 
c.       2.25 µm                               
d.      0.75 µm





   9.       A silicon PN junction at a temperature of 20oC has a reverse saturation current of 10 pico Amp. The reverse saturation current at 40oC for the same bias is approximately                      [GATE’05]


a.       30 pico Amp
b.      40 pico Amp
c.       50 pico Amp
d.      60 pico Amp





   10.   A P+N junction has a built in potential of 0.8 volts. The depletion layer width at a reverse bias of 1.2 volts is 2 µm. For a reverse bias of 7.2 volts , the depletion layer width will be :      [GATE’07]


a.       4 µm
b.      4.9 µm
c.       8 µm
d.      12 µm





   11.   A silicon PN junction is forward biased with a constant current at room temperature. When the temperature is increased by 10oC, the forward bias voltage across the PN junction          [GATE’11]


a.       Increases by 60 mV
b.      decreases by 60 mV
c.       Increases by 25 mV
d.      decreases by 25 mV


 
12.  The forward dynamic resistance of a junction diode  varies __________________ as the forward current.         [GATE'94]






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