1. A P+N junction has a built in potential of 0.8 volts. The
depletion layer width at a reverse bias of 1.2 volts is 2 µm.
For a reverse bias of 7.2 volts , the depletion layer width will be :
2. Group I lists four types of p-n junction diodes. Match each
device in group I with one of the option in group II to indicate
the bias condition of that device in its normal mode of
3. The DC current gain (β) of a BJT is 50. Assuming that the
emitter injection efficiency is 0.995, the base transport factor is :
(A) 0.980 (B) 0.985
(C) 0.990 (D) 0.995
4. Group I lists four different semiconductor devices. Match each
device in group I with its characteristic property in group II.
5. For the BJT circuit shown, assume that the β of the transistor is
very large and VBE is 0.7 volts. Then the mode of operation of
the BJT is :
7. For the zener diode shown in the figure, the zener voltage at
knee is 7 volts, the knee current is negligible and the zener
dynamic resistance is 10Ω. If the input voltage (Vi) range is
10 to 16 volts, the output voltage (VO) ranges from
Common Data for Questions 8, 9 and 10.
The figure shows the high frequency capacitance –voltage (C-V)
characteristics of Metal / SiO2 / silicon (MOS) capacitor having an
area of 1 x 10-4 cm2 . assume that the permittivity’s (ƐoƐr) of silicon
and Sio2 are 1x10-12 F/cm and 3.5 x 10-13 F/cm respectively.
8. The gate oxide thickness in the MOS capacitor is :
9. The maximum depletion layer width in silicon is
10. Consider the following statements about the C-V
characteristics plot :
S1 : The MOS capacitor has an n-type substrate.
S2 : If the positive charges are introduced in the oxide, the
C-V plot will shift to the left.
Then which one of the following is TRUE.