Tuesday, 11 June 2013

Video Solutions for GATE 1999 ECE : Five Mark Questions ( Electron Devices )

1. In the CMOS inverter circuit shown in figure, the input Vi makes 

    a transition from VOL (= 0 volts) to VOH (= 5 volts). 
    Determine the High to Low propagation delay time (tpHL)

    when it is driving a capacitive load (CL) of 20 pF. 

    Device data :

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