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Tuesday, 11 June 2013
Video Solutions for GATE 1999 ECE : Five Mark Questions ( Electron Devices )
1. In the CMOS inverter circuit shown in figure, the input Vi makes
a transition from V
OL
(= 0 volts) to V
OH
(= 5 volts).
Determine the High to Low propagation delay time (tp
HL
)
when it is driving a capacitive load (C
L
) of 20 pF.
Device data :
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